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ASPLOS
2009
ACM
15 years 11 months ago
Mixed-mode multicore reliability
Future processors are expected to observe increasing rates of hardware faults. Using Dual-Modular Redundancy (DMR), two cores of a multicore can be loosely coupled to redundantly ...
Philip M. Wells, Koushik Chakraborty, Gurindar S. ...
102
Voted
TLDI
2009
ACM
108views Formal Methods» more  TLDI 2009»
15 years 7 months ago
Secure compilation of a multi-tier web language
Storing state in the client tier (in forms or cookies, for example) improves the efficiency of a web application, but it also renders the secrecy and integrity of stored data vul...
Ioannis G. Baltopoulos, Andrew D. Gordon
90
Voted
CODES
2007
IEEE
15 years 4 months ago
Performance modeling for early analysis of multi-core systems
Performance analysis of microprocessors is a critical step in defining the microarchitecture, prior to register-transfer-level (RTL) design. In complex chip multiprocessor systems...
Reinaldo A. Bergamaschi, Indira Nair, Gero Dittman...
81
Voted
GLVLSI
2010
IEEE
164views VLSI» more  GLVLSI 2010»
15 years 3 months ago
Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs
On-chip memory organization is one of the most important aspects that can influence the overall system behavior in multiprocessor systems. Following the trend set by high-perform...
Mohamed M. Sabry, Martino Ruggiero, Pablo Garcia D...
113
Voted
ASPLOS
2012
ACM
13 years 6 months ago
Architectural support for hypervisor-secure virtualization
Virtualization has become a standard part of many computer systems. A key part of virtualization is the all-powerful hypervisor which manages the physical platform and can access ...
Jakub Szefer, Ruby B. Lee