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SIGMETRICS
2009
ACM
134views Hardware» more  SIGMETRICS 2009»
15 years 6 months ago
DRAM errors in the wild: a large-scale field study
Errors in dynamic random access memory (DRAM) are a common form of hardware failure in modern compute clusters. Failures are costly both in terms of hardware replacement costs and...
Bianca Schroeder, Eduardo Pinheiro, Wolf-Dietrich ...
ISLPED
2006
ACM
117views Hardware» more  ISLPED 2006»
15 years 5 months ago
Energy/power breakdown of pipelined nanometer caches (90nm/65nm/45nm/32nm)
As transistors continue to scale down into the nanometer regime, device leakage currents are becoming the dominant cause of power dissipation in nanometer caches, making it essent...
Samuel Rodríguez, Bruce L. Jacob
GLVLSI
2005
IEEE
124views VLSI» more  GLVLSI 2005»
15 years 5 months ago
A first look at the interplay of code reordering and configurable caches
The instruction cache is a popular target for optimizations of microprocessor-based systems because of the cache’s high impact on system performance and power, and because of th...
Ann Gordon-Ross, Frank Vahid, Nikil Dutt
ATAL
2005
Springer
15 years 5 months ago
A comparative evaluation of agent location mechanisms in large scale MAS
Agents in open multi-agent systems (MAS) need means for locating other agents with which they may collaborate. To address this need, several agent location mechanisms were suggest...
David Ben-Ami, Onn Shehory
SMA
2003
ACM
120views Solid Modeling» more  SMA 2003»
15 years 5 months ago
Three-dimensional halfspace constructive solid geometry tree construction from implicit boundary representations
This paper presents a new method to compute constructive solid geometry (CSG) tree representations of an object whose faces consist of planar and non-planar surfaces. The algorith...
Suzanne F. Buchele, Richard H. Crawford