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PATMOS
2004
Springer
15 years 5 months ago
Sleepy Stack Reduction of Leakage Power
Leakage power consumption of current CMOS technology is already a great challenge. ITRS projects that leakage power consumption may come to dominate total chip power consumption as...
Jun-Cheol Park, Vincent John Mooney III, Philipp P...
MOBIDE
2003
ACM
15 years 5 months ago
TiNA: a scheme for temporal coherency-aware in-network aggregation
This paper presents TiNA, a scheme for minimizing energy consumption in sensor networks by exploiting end-user tolerance to temporal coherency. TiNA utilizes temporal coherency to...
Mohamed A. Sharaf, Jonathan Beaver, Alexandros Lab...
SC
2003
ACM
15 years 5 months ago
Parallel Multilevel Sparse Approximate Inverse Preconditioners in Large Sparse Matrix Computations
We investigate the use of the multistep successive preconditioning strategies (MSP) to construct a class of parallel multilevel sparse approximate inverse (SAI) preconditioners. W...
Kai Wang, Jun Zhang, Chi Shen
ISSS
2002
IEEE
103views Hardware» more  ISSS 2002»
15 years 4 months ago
A Symbolic Approach for the Combined Solution of Scheduling and Allocation
Scheduling is widely recognized as a very important step in highlevel synthesis. Nevertheless, it is usually done without taking into account the effects on the actual hardware im...
Luciano Lavagno, Mihai T. Lazarescu, Stefano Quer,...
ISSS
2002
IEEE
148views Hardware» more  ISSS 2002»
15 years 4 months ago
A Case Study of Hardware and Software Synthesis in ForSyDe
ForSyDe (FORmal SYstem DEsign) is a methodology which addresses the design of SoC applications which may contain control as well as data flow dominated parts. Starting with a for...
Ingo Sander, Axel Jantsch, Zhonghai Lu