Leakage power consumption of current CMOS technology is already a great challenge. ITRS projects that leakage power consumption may come to dominate total chip power consumption as...
Jun-Cheol Park, Vincent John Mooney III, Philipp P...
This paper presents TiNA, a scheme for minimizing energy consumption in sensor networks by exploiting end-user tolerance to temporal coherency. TiNA utilizes temporal coherency to...
Mohamed A. Sharaf, Jonathan Beaver, Alexandros Lab...
We investigate the use of the multistep successive preconditioning strategies (MSP) to construct a class of parallel multilevel sparse approximate inverse (SAI) preconditioners. W...
Scheduling is widely recognized as a very important step in highlevel synthesis. Nevertheless, it is usually done without taking into account the effects on the actual hardware im...
Luciano Lavagno, Mihai T. Lazarescu, Stefano Quer,...
ForSyDe (FORmal SYstem DEsign) is a methodology which addresses the design of SoC applications which may contain control as well as data flow dominated parts. Starting with a for...