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CODES
2007
IEEE
15 years 4 months ago
Secure FPGA circuits using controlled placement and routing
In current Field-Programmable-Logic Architecture (FPGA) design flows, it is very hard to control the routing of submodules. It is thus very hard to make an identical copy of an ex...
Pengyuan Yu, Patrick Schaumont
GLVLSI
2005
IEEE
147views VLSI» more  GLVLSI 2005»
15 years 3 months ago
1-V 7-mW dual-band fast-locked frequency synthesizer
This paper presents a fully integrated 1-V, dual band, fastlocked frequency synthesizer for IEEE 802.11 a/b/g WLAN applications. It can synthesize frequencies in the range of 2.4 ...
Vikas Sharma, Chien-Liang Chen, Chung-Ping Chen
INFOCOM
2005
IEEE
15 years 3 months ago
TCAM-based distributed parallel packet classification algorithm with range-matching solution
Packet Classification (PC) has been a critical data path function for many emerging networking applications. An interesting approach is the use of TCAM to achieve deterministic, hi...
Kai Zheng, Hao Che, Zhijun Wang, Bin Liu
SBCCI
2005
ACM
123views VLSI» more  SBCCI 2005»
15 years 3 months ago
Fault tolerance overhead in network-on-chip flow control schemes
Flow control mechanisms in Network-on-Chip (NoC) architectures are critical for fast packet propagation across the network and for low idling of network resources. Buffer manageme...
Antonio Pullini, Federico Angiolini, Davide Bertoz...
ATAL
2005
Springer
15 years 3 months ago
Bounded model checking knowledge and branching time in synchronous multi-agent systems
We present an approach to the verification of temporal epistemic properties in synchronous multi-agent systems (MAS) via bounded model checking (BMC). Based on the semantics of s...
Xiangyu Luo, Kaile Su, Abdul Sattar, Qingliang Che...