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IPPS
2009
IEEE
15 years 4 months ago
Power-aware dynamic task scheduling for heterogeneous accelerated clusters
Recent accelerators such as GPUs achieve better cost-performance and watt-performance ratio, while the range of their application is more limited than general CPUs. Thus heterogen...
Tomoaki Hamano, Toshio Endo, Satoshi Matsuoka
TPDS
1998
122views more  TPDS 1998»
14 years 9 months ago
Managing Statistical Behavior of Large Data Sets in Shared-Nothing Architectures
—Increasingly larger data sets are being stored in networked architectures. Many of the available data structures are not easily amenable to parallel realizations. Hashing scheme...
Isidore Rigoutsos, Alex Delis
ICCD
2005
IEEE
119views Hardware» more  ICCD 2005»
15 years 6 months ago
Deployment of Better Than Worst-Case Design: Solutions and Needs
The advent of nanometer feature sizes in silicon fabrication has triggered a number of new design challenges for computer designers. These challenges include design complexity and...
Todd M. Austin, Valeria Bertacco
ICCAD
2003
IEEE
132views Hardware» more  ICCAD 2003»
15 years 6 months ago
A Sum-over-Paths Impulse-Response Moment-Extraction Algorithm for IC-Interconnect Networks: Verification, Coupled RC Lines
We have created a stochastic impulse-response (IR) momentextraction algorithm for RC circuit networks. It employs a newly discovered Feynman Sum-over-Paths Postulate. Full paralle...
Yannick L. Le Coz, Dhivya Krishna, Dusan M. Petran...
ISLPED
2009
ACM
108views Hardware» more  ISLPED 2009»
15 years 2 months ago
Technology flavor selection and adaptive techniques for timing-constrained 45nm subthreshold circuits
We investigate techniques to design 45nm minimum-energy subthreshold CMOS circuits under timing constraints, considering the practical case of an 8-bit multiplier. We first show ...
David Bol, Denis Flandre, Jean-Didier Legat