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CC
2010
Springer
190views System Software» more  CC 2010»
15 years 7 months ago
Is Reuse Distance Applicable to Data Locality Analysis on Chip Multiprocessors?
On Chip Multiprocessors (CMP), it is common that multiple cores share certain levels of cache. The sharing increases the contention in cache and memory-to-chip bandwidth, further h...
Yunlian Jiang, Eddy Z. Zhang, Kai Tian, Xipeng She...
104
Voted
ISCA
2006
IEEE
162views Hardware» more  ISCA 2006»
15 years 6 months ago
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory
Long interconnects are becoming an increasingly important problem from both power and performance perspectives. This motivates designers to adopt on-chip network-based communicati...
Feihui Li, Chrysostomos Nicopoulos, Thomas D. Rich...
116
Voted
MONET
2006
129views more  MONET 2006»
15 years 17 days ago
Enabling Intelligent Handovers in Heterogeneous Wireless Networks
In the future Wireless Internet, mobile nodes will be able to choose between providers offering competing services at a much finer granularity than we find today. Rather than month...
Robert C. Chalmers, Govind Krishnamurthi, Kevin C....
ISPASS
2007
IEEE
15 years 7 months ago
DRAM-Level Prefetching for Fully-Buffered DIMM: Design, Performance and Power Saving
We have studied DRAM-level prefetching for the fully buffered DIMM (FB-DIMM) designed for multi-core processors. FB-DIMM has a unique two-level interconnect structure, with FB-DIM...
Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Zhao Zhan...
EURONGI
2004
Springer
15 years 4 months ago
Performance of Different Proxy Concepts in UMTS Networks
It is well known that the large round trip time and the highly variable delay in a cellular network may degrade the performance of TCP. Many concepts have been proposed to improve ...
Marc Necker, Michael Scharf, Andreas Weber 0003