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2008
IEEE
163views Hardware» more  DATE 2008»
16 years 1 months ago
Design flow for embedded FPGAs based on a flexible architecture template
Modern digital signal processing applications have an increasing demand for computational power while needing to preserve low power dissipation and high flexibility. For many appl...
B. Neumann, Thorsten von Sydow, Holger Blume, Tobi...
FOCS
2008
IEEE
16 years 1 months ago
Kakeya Sets, New Mergers and Old Extractors
A merger is a probabilistic procedure which extracts the randomness out of any (arbitrarily correlated) set of random variables, as long as one of them is uniform. Our main result...
Zeev Dvir, Avi Wigderson
CODES
2007
IEEE
16 years 1 months ago
Performance modeling for early analysis of multi-core systems
Performance analysis of microprocessors is a critical step in defining the microarchitecture, prior to register-transfer-level (RTL) design. In complex chip multiprocessor systems...
Reinaldo A. Bergamaschi, Indira Nair, Gero Dittman...
INFOCOM
2007
IEEE
16 years 1 months ago
Separability and Topology Control of Quasi Unit Disk Graphs
— A deep understanding of the structural properties of wireless networks is critical for evaluating the performance of network protocols and improving their designs. Many protoco...
Jianer Chen, Anxiao Jiang, Iyad A. Kanj, Ge Xia, F...
INFOCOM
2007
IEEE
16 years 1 months ago
Face Tracing Based Geographic Routing in Nonplanar Wireless Networks
— Scalable and efficient routing is a main challenge in the deployment of large ad hoc wireless networks. An essential element of practical routing protocols is their accommodat...
Fenghui Zhang, Hao Li, Anxiao Jiang, Jianer Chen, ...
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