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DAC
2009
ACM
15 years 11 months ago
Clock skew optimization via wiresizing for timing sign-off covering all process corners
Manufacturing process variability impacts the performance of synchronous logic circuits by means of its effect on both clock network and functional block delays. Typically, varia...
Sari Onaissi, Khaled R. Heloue, Farid N. Najm
DAC
2009
ACM
15 years 11 months ago
Accurate temperature estimation using noisy thermal sensors
Multicore SOCs rely on runtime thermal measurements using on-chip sensors for DTM. In this paper we address the problem of estimating the actual temperature of on-chip thermal sen...
Yufu Zhang, Ankur Srivastava
ISPD
2009
ACM
141views Hardware» more  ISPD 2009»
15 years 11 months ago
A faster approximation scheme for timing driven minimum cost layer assignment
As VLSI technology moves to the 65nm node and beyond, interconnect delay greatly limits the circuit performance. As a critical component in interconnect synthesis, layer assignmen...
Shiyan Hu, Zhuo Li, Charles J. Alpert
PLDI
2009
ACM
15 years 11 months ago
Dynamic software updates: a VM-centric approach
Software evolves to fix bugs and add features. Stopping and restarting programs to apply changes is inconvenient and often costly. Dynamic software updating (DSU) addresses this ...
Suriya Subramanian, Michael W. Hicks, Kathryn S. M...
PLDI
2009
ACM
15 years 11 months ago
Binary analysis for measurement and attribution of program performance
Modern programs frequently employ sophisticated modular designs. As a result, performance problems cannot be identified from costs attributed to routines in isolation; understand...
Nathan R. Tallent, John M. Mellor-Crummey, Michael...
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