Sciweavers

2266 search results - page 74 / 454
» Generalizing parametric timing analysis
Sort
View
129
Voted
TPDS
1998
118views more  TPDS 1998»
15 years 3 months ago
Optimizing Computing Costs Using Divisible Load Analysis
—A bus oriented network where there is a charge for the amount of divisible load processed on each processor is investigated. A cost optimal processor sequencing result is found ...
Jeeho Sohn, Thomas G. Robertazzi, Serge Luryi
ECRTS
2007
IEEE
15 years 10 months ago
A Delay Composition Theorem for Real-Time Pipelines
Uniprocessor schedulability theory made great strides, in part, due to the simplicity of composing the delay of a job from the execution times of higher-priority jobs that preempt...
Praveen Jayachandran, Tarek F. Abdelzaher
136
Voted
ISQED
2009
IEEE
126views Hardware» more  ISQED 2009»
15 years 10 months ago
Robust differential asynchronous nanoelectronic circuits
Abstract — Nanoelectronic design faces unprecedented reliability challenges and must achieve noise immunity and delay insensitiveness in the presence of prevalent defects and sig...
Bao Liu
140
Voted
DATE
2006
IEEE
91views Hardware» more  DATE 2006»
15 years 7 months ago
Efficient incremental clock latency scheduling for large circuits
The clock latency scheduling problem is usually solved on the sequential graph, also called register-to-register graph. In practice, the the extraction of the sequential graph for...
Christoph Albrecht
128
Voted
ISPD
2006
ACM
90views Hardware» more  ISPD 2006»
15 years 10 months ago
Fast buffer insertion considering process variations
Advanced process technologies call for a proactive consideration of process variations in design to ensure high parametric timing yield. Despite of its popular use in almost any h...
Jinjun Xiong, Lei He