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DATE
1998
IEEE
92views Hardware» more  DATE 1998»
15 years 9 months ago
Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques
A new approach for sequential circuit test generation is proposed that combines software testing based techniques at the high level with test enhancement techniques at the gate le...
Elizabeth M. Rudnick, Roberto Vietti, Akilah Ellis...
IFL
1999
Springer
117views Formal Methods» more  IFL 1999»
15 years 9 months ago
On Code Generation for Multi-generator WITH-Loops in SAC
Abstract. Most array operations in Sac are specified in terms of so-called withloops, a Sac-specific form of array comprehension. Due to the map-like semantics of with-loops its ...
Clemens Grelck, Dietmar Kreye, Sven-Bodo Scholz
ICRA
1998
IEEE
110views Robotics» more  ICRA 1998»
15 years 9 months ago
Generating Robust Trajectories in the Presence of Ordinary and Linear-Self-Motion Singularities
An algorithm is presented which computes feasible manipulator trajectories along fixed paths in the presence of kinematic singularities. The resulting trajectories are close to mi...
John E. Lloyd, Vincent Hayward
IPPS
1998
IEEE
15 years 9 months ago
Meta-heuristics for Circuit Partitioning in Parallel Test Generation
In this communication Simulated Annealing and Genetic Algorithms, are applied to the graph partitioning problem. These techniques mimic processes in statistical mechanics and biol...
Consolación Gil, Julio Ortega, Antonio F. D...
ITC
1998
IEEE
59views Hardware» more  ITC 1998»
15 years 9 months ago
Stimulus generation for built-in self-test of charge-pump phase-locked loops
Abstract - This paper addresses the issue of the stimulation of charge-pump phase-locked loops for built-in selftest applications. It is shown that three nodes of the PLL qualify f...
Benoît R. Veillette, Gordon W. Roberts