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DATE
2007
IEEE
95views Hardware» more  DATE 2007»
16 years 19 days ago
Memory bank aware dynamic loop scheduling
In a parallel system with multiple CPUs, one of the key problems is to assign loop iterations to processors. This problem, known as the loop scheduling problem, has been studied i...
Mahmut T. Kandemir, Taylan Yemliha, Seung Woo Son,...
DATE
2007
IEEE
143views Hardware» more  DATE 2007»
16 years 19 days ago
Portable multimedia SoC design: a global challenge
- The intrinsic capability brought by each new technology node opens the way to a broad range of system integration options and continuously enables new applications to be integrat...
Maurizio Paganini, Georg Kimmich, Stephane Ducrey,...
DDECS
2007
IEEE
201views Hardware» more  DDECS 2007»
16 years 19 days ago
Built in Defect Prognosis for Embedded Memories
: As scan compression replaces the traditional scan it is important to understand how it works with power. DFT MAX represents one of the two primary scan compression solutions used...
Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskaran...
GLOBECOM
2007
IEEE
16 years 18 days ago
Reliable Symbol Synchronization in Software-Driven Acoustic Sensor Networks
Abstract—Symbol synchronization in traditional hardwaredriven communication systems has relied on the transmission of training sequences of symbols just before the beginning of t...
Raja Jurdak, Antonio G. Ruzzelli, Gregory M. P. O'...
158
Voted
GLVLSI
2007
IEEE
141views VLSI» more  GLVLSI 2007»
16 years 18 days ago
Transition-activity aware design of reduction-stages for parallel multipliers
We propose an interconnect reorganization algorithm for reduction stages in parallel multipliers. It aims at minimizing power consumption for given static probabilities at the pri...
Saeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Osc...
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