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TACO
2008
130views more  TACO 2008»
15 years 18 days ago
Efficient hardware code generation for FPGAs
r acceptance of FPGAs as a computing device requires a higher level of programming abstraction. ROCCC is an optimizing C to HDL compiler. We describe the code generation approach i...
Zhi Guo, Walid A. Najjar, Betul Buyukkurt
72
Voted
JVCA
2007
93views more  JVCA 2007»
15 years 17 days ago
Gradient-based shell generation and deformation
Shell becomes popular in a variety of modeling techniques for representing small-scale features and increasing visual complexity. Current shell generation algorithms do not measur...
Jin Huang, Xinguo Liu, Haiyang Jiang, Qing Wang, H...
EMNLP
2010
14 years 10 months ago
Title Generation with Quasi-Synchronous Grammar
The task of selecting information and rendering it appropriately appears in multiple contexts in summarization. In this paper we present a model that simultaneously optimizes sele...
Kristian Woodsend, Yansong Feng, Mirella Lapata
FPL
2010
Springer
139views Hardware» more  FPL 2010»
14 years 10 months ago
Mapping Multiple Multivariate Gaussian Random Number Generators on an FPGA
A Multivariate Gaussian random number generator (MVGRNG) is an essential block for many hardware designs, including Monte Carlo simulations. These simulations are usually used in a...
Chalermpol Saiprasert, Christos-Savvas Bouganis, G...
125
Voted
TII
2010
166views Education» more  TII 2010»
14 years 7 months ago
Source-to-Source Architecture Transformation for Performance Optimization in BIP
Behavior, Interaction, Priorities (BIP) is a component framework for constructing systems from a set of atomic components by using two kinds of composition operators: interactions ...
Marius Bozga, Mohamad Jaber, Joseph Sifakis