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ITC
2002
IEEE
81views Hardware» more  ITC 2002»
15 years 5 months ago
Design Rewiring Using ATPG
—Logic optimization is the step of the very large scale integration (VLSI) design cycle where the designer performs modifications on a design to satisfy different constraints suc...
Andreas G. Veneris, Magdy S. Abadir, Mandana Amiri
KBSE
1999
IEEE
15 years 5 months ago
Controlled Natural Language Can Replace First-Order Logic
Many domain specialists are not familiar or comfortable with formal notations and formal tools like theorem provers or model generators. To address this problem we developed Attem...
Norbert E. Fuchs, Uta Schwertel, Sunna Torge
100
Voted
JAIR
2006
106views more  JAIR 2006»
15 years 20 days ago
Clause/Term Resolution and Learning in the Evaluation of Quantified Boolean Formulas
Resolution is the rule of inference at the basis of most procedures for automated reasoning. In these procedures, the input formula is first translated into an equisatisfiable for...
Enrico Giunchiglia, Massimo Narizzano, Armando Tac...
85
Voted
RV
2010
Springer
157views Hardware» more  RV 2010»
14 years 11 months ago
Copilot: A Hard Real-Time Runtime Monitor
Abstract. We address the problem of runtime monitoring for hard realtime programs—a domain in which correctness is critical yet has largely been overlooked in the runtime monitor...
Lee Pike, Alwyn Goodloe, Robin Morisset, Sebastian...
102
Voted
ITC
1998
IEEE
114views Hardware» more  ITC 1998»
15 years 5 months ago
BETSY: synthesizing circuits for a specified BIST environment
This paper presents a logic synthesis tool called BETSY (BIST Environment Testable Synthesis) for synthesizing circuits that achieve complete (100%)fault coverage in a user specif...
Zhe Zhao, Bahram Pouya, Nur A. Touba