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» Generating Tests from Counterexamples
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62
Voted
ICCD
2006
IEEE
84views Hardware» more  ICCD 2006»
15 years 6 months ago
Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation
—X-filling is preferred for low-capture-power scan test generation, since it reduces IR-drop-induced yield loss without the need of any circuit modification. However, the effecti...
Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Yuta Y...
83
Voted
DAC
1994
ACM
15 years 1 months ago
Functional Test Generation for FSMs by Fault Extraction
Recent results indicate that functional test pattern generation (TPG) techniques may provide better defect coverages than do traditional logic-level techniques. Functional TPG alg...
Bapiraju Vinnakota, Jason Andrews
DATE
1997
IEEE
109views Hardware» more  DATE 1997»
15 years 1 months ago
Sequential circuit test generation using dynamic state traversal
A new method for state justi cation is proposed for sequential circuit test generation. The linear list of states dynamically obtained during the derivation of test vectors is use...
Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. P...
EVOW
2009
Springer
15 years 28 days ago
Testing Detector Parameterization Using Evolutionary Exploit Generation
Abstract. The testing of anomaly detectors is considered from the perspective of a Multi-objective Evolutionary Exploit Generator (EEG). Such a framework provides users of anomaly ...
Hilmi Günes Kayacik, A. Nur Zincir-Heywood, M...
VTS
1998
IEEE
88views Hardware» more  VTS 1998»
15 years 1 months ago
Transition Maximization Techniques for Enhancing the Two-Pattern Fault Coverage of Pseudorandom Test Pattern Generators
This paper presents simulation evidence supporting the use of bit transition maximization techniques in the design of hardware test pattern generators TPGs. Bit transition maximiz...
Bruce F. Cockburn, Albert L.-C. Kwong