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» Generating Unit Tests from Formal Proofs
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EURODAC
1994
IEEE
145views VHDL» more  EURODAC 1994»
15 years 1 months ago
Testability analysis and improvement from VHDL behavioral specifications
This paper presents a testability improvement method for digital systems described in VHDL behavioral specification. The method is based on testability analysis at registertransfe...
Xinli Gu, Krzysztof Kuchcinski, Zebo Peng
JOT
2007
123views more  JOT 2007»
14 years 9 months ago
Towards a Tool Supporting Integration Testing of Aspect-Oriented Programs
Aspect-Oriented Programming is an emerging software engineering paradigm. It offers new constructs and tools improving separation of crosscutting concerns into single units called...
Philippe Massicotte, Linda Badri, Mourad Badri
87
Voted
KBSE
2008
IEEE
15 years 4 months ago
Type-Checking Software Product Lines - A Formal Approach
—A software product line (SPL) is an efficient means to generate a family of program variants for a domain from a single code base. However, because of the potentially high numb...
Christian Kästner, Sven Apel
RE
2008
Springer
14 years 9 months ago
Generating Natural Language specifications from UML class diagrams
Early phases of software development are known to be problematic, difficult to manage and errors occurring during these phases are expensive to correct. Many systems have been deve...
Farid Meziane, Nikos Athanasakis, Sophia Ananiadou
TPHOL
2008
IEEE
15 years 4 months ago
The Isabelle Framework
g to the well-known “LCF approach” of secure inferences as abstract datatype constructors in ML [16]; explicit proof terms are also available [8]. Isabelle/Isar provides sophis...
Makarius Wenzel, Lawrence C. Paulson, Tobias Nipko...