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» Generating VHDL models from natural language descriptions
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EVOW
2001
Springer
15 years 6 months ago
ARPIA: A High-Level Evolutionary Test Signal Generator
The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective faul...
Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda...
ICGI
2010
Springer
15 years 2 months ago
Enhanced Suffix Arrays as Language Models: Virtual k-Testable Languages
Abstract. In this article, we propose the use of suffix arrays to efficiently implement n-gram language models with practically unlimited size n. This approach, which is used with ...
Herman Stehouwer, Menno van Zaanen
WSC
2007
15 years 3 months ago
How to synthesize nets from languages: a survey
In this paper we present a survey on methods for the synthesis of Petri nets from behavioral descriptions given as languages. We consider place/transition Petri nets, elementary P...
Robert Lorenz, Sebastian Mauser, Gabriel Juh&aacut...
SAIG
2000
Springer
15 years 5 months ago
Generating Data Analysis Programs from Statistical Models
Extracting information from data, often also called data analysis, is an important scienti c task. Statistical approaches, which use methods from probability theory and numerical a...
Bernd Fischer 0002, Johann Schumann, Thomas Pressb...
ENGL
2008
100views more  ENGL 2008»
15 years 1 months ago
HIDE+: A Logic Based Hardware Development Environment
With the advent of System-On-Chip (SOC) technology, there is a pressing need to enhance the quality of ools available and increase the level of abstraction at which hardware is des...
Abdsamad Benkrid, Khaled Benkrid