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» Generating compilers for generated datapaths
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FPGA
2001
ACM
123views FPGA» more  FPGA 2001»
15 years 7 months ago
Matching and searching analysis for parallel hardware implementation on FPGAs
Matching and searching computations play an important role in the indexing of data. These computations are typically encoded in very tight loops with a single index variable and a...
Pablo Moisset, Pedro C. Diniz, Joonseok Park
IEEEPACT
2000
IEEE
15 years 7 months ago
Global Register Partitioning
Modern computers have taken advantage of the instruction-level parallelism (ILP) available in programs with advances in both architecture and compiler design. Unfortunately, large...
Jason Hiser, Steve Carr, Philip H. Sweany
ISCA
1999
IEEE
94views Hardware» more  ISCA 1999»
15 years 7 months ago
Storageless Value Prediction Using Prior Register Values
This paper presents a technique called register value prediction (RVP) which uses a type of locality called register-value reuse. By predicting that an instruction will produce th...
Dean M. Tullsen, John S. Seng
IWPC
1999
IEEE
15 years 7 months ago
Recovery of Jump Table Case Statements from Binary Code
One of the fundamental problems with the static analysis of binary (executable) code is that7 of recognizing, in a machine-independent way, the target addresses of n-conditional b...
Cristina Cifuentes, Mike Van Emmerik
LCTRTS
1999
Springer
15 years 7 months ago
Effective Exploitation of a Zero Overhead Loop Buffer
A Zero Overhead Loop Buffer (ZOLB) is an architectural feature that is commonly found in DSP processors. This buffer can be viewed as a compiler managed cache that contains a sequ...
Gang-Ryung Uh, Yuhong Wang, David B. Whalley, Sanj...