Sciweavers

1140 search results - page 171 / 228
» Generating compilers for generated datapaths
Sort
View
137
Voted
SIGPLAN
2002
15 years 2 months ago
Write barrier removal by static analysis
We present a new analysis for removing unnecessary write barriers in programs that use generational garbage collection. To our knowledge, this is the first static program analysis...
Karen Zee, Martin C. Rinard
146
Voted
ISCA
2011
IEEE
313views Hardware» more  ISCA 2011»
14 years 6 months ago
FabScalar: composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template
A growing body of work has compiled a strong case for the single-ISA heterogeneous multi-core paradigm. A single-ISA heterogeneous multi-core provides multiple, differently-design...
Niket Kumar Choudhary, Salil V. Wadhavkar, Tanmay ...
DAC
1999
ACM
16 years 4 months ago
Synthesis of Embedded Software Using Free-Choice Petri Nets
Software synthesis from a concurrent functional specification is a key problem in the design of embedded systems. A concurrent specification is well-suited for medium-grained part...
Marco Sgroi, Luciano Lavagno
DAC
2003
ACM
16 years 4 months ago
Clock-tree power optimization based on RTL clock-gating
As power consumption of the clock tree in modern VLSI designs tends to dominate, measures must be taken to keep it under control. This paper introduces an approach for reducing cl...
Monica Donno, Alessandro Ivaldi, Luca Benini, Enri...
ICSE
2009
IEEE-ACM
16 years 4 months ago
Analyzing critical process models through behavior model synthesis
Process models capture tasks performed by agents together with their control flow. Building and analyzing such models is important but difficult in certain areas such as safety-cr...
Christophe Damas, Bernard Lambeau, Francois Roucou...