Sciweavers

1140 search results - page 4 / 228
» Generating compilers for generated datapaths
Sort
View
DATE
2005
IEEE
169views Hardware» more  DATE 2005»
15 years 3 months ago
Optimized Generation of Data-Path from C Codes for FPGAs
Zhi Guo, Betul Buyukkurt, Walid A. Najjar, Kees A....
62
Voted
ERSA
2003
93views Hardware» more  ERSA 2003»
14 years 11 months ago
An Improved Intermediate Representation for Datapath Generation
Nico Kasprzyk, Andreas Koch, Ulrich Golze, Michael...
TCAD
2002
129views more  TCAD 2002»
14 years 9 months ago
Analytical approach to layout generation of datapath cells
Maciej J. Ciesielski, Serkan Askar, Samuel Levitin
88
Voted
DATE
2008
IEEE
168views Hardware» more  DATE 2008»
15 years 4 months ago
Cycle-approximate Retargetable Performance Estimation at the Transaction Level
This paper presents a novel cycle-approximate performance estimation technique for automatically generated transaction level models (TLMs) for heterogeneous multicore designs. The...
Yonghyun Hwang, Samar Abdi, Daniel Gajski
ICCAD
1994
IEEE
110views Hardware» more  ICCAD 1994»
15 years 1 months ago
Test pattern generation based on arithmetic operations
Existing built-in self test (BIST) strategies require the use of specialized test pattern generation hardware which introduces signi cant area overhead and performance degradation...
Sanjay Gupta, Janusz Rajski, Jerzy Tyszer