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» Generating compilers for generated datapaths
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VTS
2007
IEEE
135views Hardware» more  VTS 2007»
15 years 9 months ago
High Level Synthesis of Degradable ASICs Using Virtual Binding
—As the complexity of the integrated circuits increases, they become more susceptible to manufacturing faults, decreasing the total process yield. Thus, it would be desirable to ...
Nima Honarmand, A. Shahabi, Hasan Sohofi, Maghsoud...
DSN
2006
IEEE
15 years 9 months ago
In-Register Duplication: Exploiting Narrow-Width Value for Improving Register File Reliability
Protecting the register value and its data buses is crucial to reliable computing in high-performance microprocessors due to the increasing susceptibility of CMOS circuitry to sof...
Jie Hu, Shuai Wang, Sotirios G. Ziavras
ISSS
2002
IEEE
176views Hardware» more  ISSS 2002»
15 years 8 months ago
Controller Estimation for FPGA Target Architectures during High-Level Synthesis
In existing synthesis systems, the influence of the area and delay of the controller is not or not sufficiently taken into account. But the controller can have a big influence,...
Oliver Bringmann, Wolfgang Rosenstiel, Carsten Men...
ISSS
2002
IEEE
174views Hardware» more  ISSS 2002»
15 years 8 months ago
A Run-Time Word-Level Reconfigurable Coarse-Grain Functional Unit for a VLIW Processor
Nowadays, new DSP applications are offering combined and flexible multimedia and telecom services. VLIW processor architectures, which include dedicated but inflexible functional ...
Carles Rodoreda Sala, Natalino G. Busá
CODES
2000
IEEE
15 years 7 months ago
Heuristic tradeoffs between latency and energy consumption in register assignment
One of the challenging tasks in code generation for embedded systems is register allocation and assignment, wherein one decides on the placement and lifetimes of variables in regi...
R. Anand, Margarida F. Jacome, Gustavo de Veciana