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ICCAD
2005
IEEE
106views Hardware» more  ICCAD 2005»
15 years 6 months ago
New decompilation techniques for binary-level co-processor generation
—Existing ASIPs (application-specific instruction-set processors) and compiler-based co-processor synthesis approaches meet the increasing performance requirements of embedded ap...
Greg Stiff, Frank Vahid
DATE
2009
IEEE
113views Hardware» more  DATE 2009»
15 years 4 months ago
Algorithms for the automatic extension of an instruction-set
Abstract—In this paper, two general algorithms for the automatic generation of instruction-set extensions are presented. The basic instruction set of a reconfigurable architectu...
Carlo Galuzzi, Dimitris Theodoropoulos, Roel Meeuw...
LCPC
2000
Springer
15 years 1 months ago
Improving Offset Assignment for Embedded Processors
Embedded systems consisting of the application program ROM, RAM, the embedded processor core, and any custom hardware on a single wafer are becoming increasingly common in applicat...
Sunil Atri, J. Ramanujam, Mahmut T. Kandemir
CGO
2006
IEEE
15 years 3 months ago
Constructing Virtual Architectures on a Tiled Processor
As the amount of available silicon resources on one chip increases, we have seen the advent of ever increasing parallel resources integrated on-chip. Many architectures use these ...
David Wentzlaff, Anant Agarwal
SBACPAD
2005
IEEE
176views Hardware» more  SBACPAD 2005»
15 years 3 months ago
Analyzing and Improving Clustering Based Sampling for Microprocessor Simulation
The time required to simulate a complete benchmark program using the cycle-accurate model of a microprocessor can be prohibitively high. One of the proposed methodologies, represe...
Yue Luo, Ajay Joshi, Aashish Phansalkar, Lizy Kuri...