127 search results - page 17 / 26 » Generation of Design Suggestions for Coarse-Grain Reconfigur... |
CASES
2008
ACM
14 years 11 months ago
2008
ACM
Although CMOS feature size scaling has been the source of dramatic performance gains, it has lead to mounting reliability concerns due to increasing power densities and on-chip te...
129
click to vote
ANCS
2010
ACM
14 years 7 months ago
2010
ACM
As we move forward towards the next generation of wireless protocols, the push for a better radio physical layer is ever increasing. Conventional radio architectures are limited t...
CVPR
1998
IEEE
15 years 11 months ago
1998
IEEE
We have designed and implemented a system for real-time detection of 2-D features on a reconfigurable computer based on Field Programmable Gate Arrays (FPGA `s). We envision this ...
VLSID
2009
IEEE
15 years 10 months ago
2009
IEEE
Increasing the number of cores in a multi-core processor reduces per-core performance. On the other hand, providing more resources to each core limits the number of cores on a chi...
BIBE
2007
IEEE
14 years 11 months ago
2007
IEEE
In this paper we describe our design and characterization of a co-processor architecture to accelerate median-based phylogenetic reconstruction for generearrangement data. Our curr...