185 search results - page 5 / 37 » Generation of Interpretive and Compiled Instruction Set Simu... |
CGO
2010
IEEE
15 years 4 months ago
2010
IEEE
For memory constrained embedded systems code size is at least as important as performance. One way of increasing code density is to exploit compact instruction formats, e.g. ARM T...
CODES
2007
IEEE
15 years 3 months ago
2007
IEEE
We address the problem of instruction selection for Multi-Output Instructions (MOIs), producing more than one result. Such inherently parallel hardware instructions are very commo...
121
Voted
DAC
1997
ACM
15 years 1 months ago
1997
ACM
Abstract—We present the Instruction Set Description Language, ISDL, a machine description language used to describe target architectures to a retargetable compiler. The features ...
95
Voted
FDL
2007
IEEE
15 years 3 months ago
2007
IEEE
—This paper presents Anahita Processor Description Language (APDL) for generation of retargetable processor design tool sets. The emphasis is on the applicability of the generate...
PLDI
1995
ACM
15 years 1 months ago
1995
ACM
Traditional list schedulers order instructions based on an optimistic estimate of the load latency imposed by the hardware and therefore cannot respond to variations in memory lat...