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VLSID
2002
IEEE
125views VLSI» more  VLSID 2002»
15 years 10 months ago
Software Pipelining for Coarse-Grained Reconfigurable Instruction Set Processors
This paper shows that software pipelining can be an effective technique for code generation for coarse-grained reconfigurable instruction set processors. The paper describes a tec...
Francisco Barat, Murali Jayapala, Pieter Op de Bee...
ENTCS
2007
108views more  ENTCS 2007»
14 years 9 months ago
Simulating and Compiling Code for the Sequential Quantum Random Access Machine
We present the SQRAM architecture for quantum computing, which is based on Knill’s QRAM model. We detail a suitable instruction set, which implements a universal set of quantum ...
Rajagopal Nagarajan, Nikolaos Papanikolaou, David ...
APCSAC
2001
IEEE
15 years 1 months ago
Exploiting Java Instruction/Thread Level Parallelism with Horizontal Multithreading
Java bytecodes can be executed with the following three methods: a Java interpretor running on a particular machine interprets bytecodes; a Just-In-Time (JIT) compiler translates ...
Kenji Watanabe, Wanming Chu, Yamin Li
LCTRTS
2007
Springer
15 years 3 months ago
Combining source-to-source transformations and processor instruction set extensions for the automated design-space exploration o
Industry’s demand for flexible embedded solutions providing high performance and short time-to-market has led to the development of configurable and extensible processors. The...
Richard Vincent Bennett, Alastair Colin Murray, Bj...
ISCA
2005
IEEE
128views Hardware» more  ISCA 2005»
15 years 3 months ago
An Evaluation Framework and Instruction Set Architecture for Ion-Trap Based Quantum Micro-Architectures
: The theoretical study of quantum computation has yielded efficient algorithms for some traditionally hard problems. Correspondingly, experimental work on the underlying physical...
Steven Balensiefer, Lucas Kreger-Stickles, Mark Os...