185 search results - page 7 / 37 » Generation of Interpretive and Compiled Instruction Set Simu... |
76
Voted
CODES
2006
IEEE
15 years 3 months ago
2006
IEEE
Traditionally, instruction-set simulators (ISS’s) are sequential programs running on individual processors. Besides the advances of simulation techniques, ISS’s have been main...
79
Voted
DAC
2001
ACM
15 years 10 months ago
2001
ACM
New application-focused system-on-chip platforms motivate new application-specific processors. Configurable and extensible processor architectures offer the efficiency of tuned lo...
ISCC
2009
IEEE
15 years 4 months ago
2009
IEEE
Reconfigurable computing is one of the most recent research topics in computer science. The Altera™ Nios II soft-core processor can be included in a large set of reconfigurable ...
SBCCI
2006
ACM
15 years 3 months ago
2006
ACM
The growing complexity and production cost of processor-based systems have imposed big constraints in SoC design of new systems. GPPs and ASICs are unable to fit the tight perform...
ASPDAC
2006
ACM
15 years 3 months ago
2006
ACM
– An instruction set level reference model was developed for the development of synergistic processing unit (SPU) , which is one of the key components of the cell processor [1][2...