38 search results - page 3 / 8 » Generation of Synthetic Sequential Benchmark Circuits |
ICCAD
1998
IEEE
13 years 10 months ago
1998
IEEE
A method is presented for identifying primitive path-delay faults in non-scan sequential circuits and generating robust tests for all robustly testable primitive faults. It uses t...
DATE
1998
IEEE
13 years 10 months ago
1998
IEEE
A new approach for sequential circuit test generation is proposed that combines software testing based techniques at the high level with test enhancement techniques at the gate le...
ICCAD
1998
IEEE
13 years 10 months ago
1998
IEEE
In this paper, we present results for significantly improving the performance of sequential circuit diagnostic test pattern generation (DATPG). Our improvements are achieved by de...
JISE
2000
13 years 6 months ago
2000
We present an algorithm for identifyinga set of faults that do not have to be targeted by a sequential delay fault test generator. These faults either cannot independently aect th...
ATS
1997
IEEE
13 years 10 months ago
1997
IEEE
Testing circuits which do not include a global reset signal requires either complex ATPG algorithms based on 9- or even 256-valued algebras, or some suitable method to generate in...