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FDL
2008
IEEE
14 years 12 months ago
RTL Generation of Channel Architecture Templates for a Template-based SoC Design Flow
In this paper, we propose the design methodology for communication channel templates from formal specification to RTL description. In this flow, design and verification start from...
Jinhyun Cho, Soonwoo Choi, Soo Chae
ITC
1997
IEEE
73views Hardware» more  ITC 1997»
15 years 2 months ago
A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems
In a fundamental paradigm shift in system design, entire systems are being built on a single chip, using multiple embedded cores. Though the newest system design methodology has s...
Indradeep Ghosh, Niraj K. Jha, Sujit Dey
SACRYPT
1999
Springer
15 years 2 months ago
Yarrow-160: Notes on the Design and Analysis of the Yarrow Cryptographic Pseudorandom Number Generator
We describe the design of Yarrow, a family of cryptographic pseudo-random number generators (PRNG). We describe the concept of a PRNG as a separate cryptographic primitive, and the...
John Kelsey, Bruce Schneier, Niels Ferguson
ISVLSI
2007
IEEE
181views VLSI» more  ISVLSI 2007»
15 years 4 months ago
Code-coverage Based Test Vector Generation for SystemC Designs
Abstract— Time-to-Market plays a central role on System-ona-Chip (SoC) competitiveness and the quality of the final product is a matter of concern as well. As SoCs complexity in...
Alair Dias Jr., Diógenes Cecilio da Silva J...
ITCC
2002
IEEE
15 years 3 months ago
Design and Generation of Adaptable Web Information Systems with KIWIS
Web-based Information Systems (WIS) are now widely used for diffusing and processing information over the network. Methodological guidelines which assist WIS developers in their t...
Marlène Villanova-Oliver, Jérô...