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ITC
2002
IEEE
81views Hardware» more  ITC 2002»
15 years 2 months ago
Design Rewiring Using ATPG
—Logic optimization is the step of the very large scale integration (VLSI) design cycle where the designer performs modifications on a design to satisfy different constraints suc...
Andreas G. Veneris, Magdy S. Abadir, Mandana Amiri
AGTIVE
1999
Springer
15 years 1 months ago
Support for Design Patterns Through Graph Transformation Tools
A suitable software architecture –for example in the area of distributed application– can be composed of known-to-work solutions. These are also known as design patterns. Howev...
Ansgar Radermacher
AR
2008
97views more  AR 2008»
14 years 9 months ago
Modular Architecture for Humanoid Walking Pattern Prototyping and Experiments
In this paper we describe the use of design patterns as a basis for creating a Humanoid Walking Pattern Generator Software having a modular architecture. This architecture made po...
Olivier Stasse, Björn Verrelst, Pierre-Brice ...
JOT
2007
119views more  JOT 2007»
14 years 9 months ago
Observer-Conditioned-Observable Design Pattern
The Observer-Conditioned-Observable (OCO) combines digitizing and transcoding of numeric change events. During the processing of numeric events, the transcoder converts the number...
Douglas A. Lyon, Carl F. R. Weiman
DDECS
2007
IEEE
105views Hardware» more  DDECS 2007»
15 years 4 months ago
Layout to Logic Defect Analysis for Hierarchical Test Generation
- As shown by previous studies, shorts between the interconnect wires should be considered as the predominant cause of failures in CMOS circuits. Fault models and tools for targeti...
Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A...