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DAC
2001
ACM
16 years 3 months ago
Address Code Generation for Digital Signal Processors
Sathishkumar Udayanarayanan, Chaitali Chakrabarti
ITC
1998
IEEE
114views Hardware» more  ITC 1998»
15 years 6 months ago
BETSY: synthesizing circuits for a specified BIST environment
This paper presents a logic synthesis tool called BETSY (BIST Environment Testable Synthesis) for synthesizing circuits that achieve complete (100%)fault coverage in a user specif...
Zhe Zhao, Bahram Pouya, Nur A. Touba
ACMSE
2006
ACM
15 years 8 months ago
Performance evaluation of the reactor pattern using the OMNeT++ simulator
The design of large-scale, distributed, performance-sensitive systems presents numerous challenges due to their networkcentric nature and stringent quality of service (QoS) requir...
Arundhati Kogekar, Aniruddha S. Gokhale
ECAL
2005
Springer
15 years 8 months ago
Biological Development of Cell Patterns: Characterizing the Space of Cell Chemistry Genetic Regulatory Networks
Abstract. Genetic regulatory networks (GRNs) control gene expression and are responsible for establishing the regular cellular patterns that constitute an organism. This paper intr...
Nicholas S. Flann, Jing Hu, Mayank Bansal, Vinay P...
ATS
1998
IEEE
91views Hardware» more  ATS 1998»
15 years 6 months ago
Special ATPG to Correlate Test Patterns for Low-Overhead Mixed-Mode BIST
In mixed-mode BIST, deterministic test patterns are generated with on-chip hardware to detect the random-pattern-resistant (r.p.r.) faults that are missed by the pseudo-random pat...
Madhavi Karkala, Nur A. Touba, Hans-Joachim Wunder...