Sciweavers

10700 search results - page 459 / 2140
» Generative Design Patterns
Sort
View
SBCCI
2005
ACM
185views VLSI» more  SBCCI 2005»
15 years 10 months ago
Automatic generation of test sets for SBST of microprocessor IP cores
Higher integration densities, smaller feature lengths, and other technology advances, as well as architectural evolution, have made microprocessor cores exceptionally complex. Cur...
Ernesto Sánchez, Matteo Sonza Reorda, Giova...
GLVLSI
2009
IEEE
113views VLSI» more  GLVLSI 2009»
15 years 8 months ago
Reducing parity generation latency through input value aware circuits
1 Soft errors caused by cosmic particles and radiation emitted by the packaging are an important problem in contemporary microprocessors. Parity bits are used to detect single bit ...
Yusuf Osmanlioglu, Y. Onur Koçberber, Oguz ...
ICALP
2000
Springer
15 years 8 months ago
On Message Sequence Graphs and Finitely Generated Regular MSC Languages
Message Sequence Charts (MSCs) are an attractive visual formalism widely used to capture system requirements during the early design stages in domains such as telecommunication sof...
Jesper G. Henriksen, Madhavan Mukund, K. Narayan K...
UML
2000
Springer
15 years 8 months ago
Using UML Collaboration Diagrams for Static Checking and Test Generation
Software testing can only be formalized and quanti ed when a solid basis for test generation can be de ned. Tests are commonly generated from program source code, graphical models ...
Aynur Abdurazik, A. Jefferson Offutt
FPL
2007
Springer
142views Hardware» more  FPL 2007»
15 years 10 months ago
DWARV: DelftWorkBench Automated Reconfigurable VHDL Generator
In this paper, we present the DWARV C-to-VHDL generation toolset. The toolset provides support for broad range of application domains. It exploits the operation parallelism, avail...
Yana Yankova, Koen Bertels, Georgi Kuzmanov, Georg...