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159
Voted
INFOCOM
2010
IEEE
15 years 5 months ago
2010
IEEE
Abstract—Many network processing applications require wirespeed access to large data structures or a large amount of flowlevel data, but the capacity of SRAMs is woefully inadeq...
174
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ARITH
2009
IEEE
16 years 1 months ago
2009
IEEE
Datapath synthesis for standard-cell design goes through extraction of arithmetic operations from RTL code, high-level arithmetic optimizations and netlist generation. Numerous ar...
172
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DFT
2007
IEEE
16 years 1 months ago
2007
IEEE
In the paper, a methodology of developing checkers for communication protocol testing is presented. It was used to develop checker to test IP cores communication protocol implemen...
237
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ASAP
2006
IEEE
16 years 28 days ago
2006
IEEE
Massively parallel processor array architectures can be used as hardware accelerators for a plenty of dataflow dominant applications. Bilateral filtering is an example of a stat...
139
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ISCAS
2006
IEEE
16 years 27 days ago
2006
IEEE
Abstract— This paper introduces a novel four-order system, which can generate one-directional (1-D) n−torus, twodirectional (2-D) n × m −torus, three-directional (3-D) n × ...