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CDES
2008
90views Hardware» more  CDES 2008»
15 years 6 months ago
Nanocompilation for the Cell Matrix Architecture
- The Cell Matrix Architecture is a massive array of dynamically self-configurable, uniformly connected, identical computational units. This architecture can enable efficient, prac...
Thomas Way, Rushikesh Katikar, Ch. Purushotham
HPDC
2005
IEEE
15 years 10 months ago
Genetic algorithm based automatic data partitioning scheme for HPF
good data partitioning scheme is the need of the time. However it is very diflcult to arrive at a good solution as the number of possible dutupartitionsfor a given real lifeprogra...
Sunil Kumar Anand, Y. N. Srikant
SAC
2008
ACM
15 years 4 months ago
A hybrid software-based self-testing methodology for embedded processor
Software-based self-test (SBST) is emerging as a promising technology for enabling at-speed testing of high-speed embedded processors testing in an SoC system. For SBST, test rout...
Tai-Hua Lu, Chung-Ho Chen, Kuen-Jong Lee
CDES
2006
184views Hardware» more  CDES 2006»
15 years 6 months ago
Compilation for Future Nanocomputer Architectures
Compilation has a long history of translating a programmer's human-readable code into machine instructions designed to make good use of a specific target computer. In this pa...
Thomas P. Way
IFIP
1999
Springer
15 years 9 months ago
A Synthesis Algorithm for Modular Design of Pipelined Circuits
: This paper presents a synthesis algorithm for pipelined circuits. The circuit is specified as a collection of independent, looselycoupled modules connected by queues. The synthe...
Maria-Cristina V. Marinescu, Martin C. Rinard