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99
Voted
ICCD
2008
IEEE
124views Hardware» more  ICCD 2008»
15 years 11 months ago
Global bus route optimization with application to microarchitectural design exploration
— Circuit and processor designs will continue to increase in complexity for the foreseeable future. With these increasing sizes comes the use of wide buses to move large amounts ...
Dae Hyun Kim, Sung Kyu Lim
113
Voted
ICCD
2004
IEEE
106views Hardware» more  ICCD 2004»
15 years 11 months ago
Gate Sizing and V{t} Assignment for Active-Mode Leakage Power Reduction
Leakage current is a key factor in IC power consumption even in the active operating mode. We investigate the simultaneous optimization of gate size and threshold voltage to reduc...
Feng Gao, John P. Hayes
123
Voted
ICCD
2002
IEEE
140views Hardware» more  ICCD 2002»
15 years 11 months ago
Fitted Elmore Delay: A Simple and Accurate Interconnect Delay Model
— In this paper, we present a new interconnect delay model called Fitted Elmore delay (FED). FED is generated by approximating Hspice delay data using a curve fitting technique....
Arif Ishaq Abou-Seido, Brian Nowak, Chris C. N. Ch...
ICCAD
2008
IEEE
162views Hardware» more  ICCAD 2008»
15 years 11 months ago
MAPS: multi-algorithm parallel circuit simulation
— The emergence of multi-core and many-core processors has introduced new opportunities and challenges to EDA research and development. While the availability of increasing paral...
Xiaoji Ye, Wei Dong, Peng Li, Sani R. Nassif
116
Voted
APSEC
2009
IEEE
15 years 9 months ago
Directed Test Suite Augmentation
Abstract—As software evolves, engineers use regression testing to evaluate its fitness for release. Such testing typically begins with existing test cases, and many techniques h...
Zhihong Xu, Gregg Rothermel