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SIGGRAPH
1999
ACM
15 years 6 months ago
Optimization of Mesh Locality for Transparent Vertex Caching
Bus traffic between the graphics subsystem and memory can become a bottleneck when rendering geometrically complex meshes. In this paper, we investigate the use of vertex caching...
Hugues Hoppe
ISSS
1999
IEEE
168views Hardware» more  ISSS 1999»
15 years 6 months ago
Automatic Architectural Synthesis of VLIW and EPIC Processors
This paper describes a mechanism for automatic design and synthesis of very long instruction word (VLIW), and its generalization, explicitly parallel instruction computing rocesso...
Shail Aditya, B. Ramakrishna Rau, Vinod Kathail
EUROMICRO
1998
IEEE
15 years 6 months ago
System Level Modelling for Hardware/Software Systems
Industry is facing a crisis in the design of complex hardware/software systems. Due to the increasing complexity, the gap between the generation of a product idea and the realisat...
Jeroen Voeten, P. H. A. van der Putten, Marc Geile...
ICCAD
1998
IEEE
95views Hardware» more  ICCAD 1998»
15 years 6 months ago
Efficient analog circuit synthesis with simultaneous yield and robustness optimization
This paper presents an efficient statistical design methodology that allows simultaneous sizing for performance and optimization for yield and robustness of analog circuits. The s...
Geert Debyser, Georges G. E. Gielen
SPW
1999
Springer
15 years 6 months ago
Performance of Protocols
This paper presents a comprehensive study on the performance of common MANET (mobile ad hoc network) routing protocols under realistic network scenarios. The routing protocols use...
Michael Roe