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CF
2010
ACM
15 years 2 months ago
Enabling a highly-scalable global address space model for petascale computing
Over the past decade, the trajectory to the petascale has been built on increased complexity and scale of the underlying parallel architectures. Meanwhile, software developers hav...
Vinod Tipparaju, Edoardo Aprà, Weikuan Yu, ...
93
Voted
AINA
2010
IEEE
14 years 6 months ago
Neural Network Trainer through Computer Networks
- This paper introduces a neural network training tool through computer networks. The following algorithms, such as neuron by neuron (NBN) [1][2], error back propagation (EBP), Lev...
Nam Pham, Hao Yu, Bogdan M. Wilamowski
SEUS
2007
IEEE
15 years 3 months ago
A Framework for Hardware-in-the-Loop Testing of an Integrated Architecture
In this paper we present a distributed Hardware-in-the-Loop (HiL) simulation approach that supports the verification and validation activities in an integrated architecture as rec...
Martin Schlager, Roman Obermaisser, Wilfried Elmen...
ICS
1999
Tsinghua U.
15 years 1 months ago
Fast cluster failover using virtual memory-mapped communication
This paper proposes a novel way to use virtual memorymapped communication (VMMC) to reduce the failover time on clusters. With the VMMC model, applications’ virtual address spac...
Yuanyuan Zhou, Peter M. Chen, Kai Li
FCCM
2004
IEEE
118views VLSI» more  FCCM 2004»
15 years 1 months ago
Virtual Memory Window for a Portable Reconfigurable Cryptography Coprocessor
Reconfigurable System-on-Chip (SoC) platforms that incorporate hard-core processors surrounded by large amounts of FPGA are today commodities: the reconfigurable logic is often us...
Miljan Vuletic, Laura Pozzi, Paolo Ienne