58 search results - page 7 / 12 » Generic fuzzy logic CAD development tool |
FPGA
2005
ACM
15 years 3 months ago
2005
ACM
Creating a new FPGA is a challenging undertaking because of the significant effort that must be spent on circuit design, layout and verification. It currently takes approximately ...
DAC
2008
ACM
15 years 10 months ago
2008
ACM
FPGA application developers often attempt to use pipelining, Cslowing and retiming to improve the performance of their designs. Unfortunately, such registered netlists present a f...
GLVLSI
2007
IEEE
15 years 4 months ago
2007
IEEE
We propose an interconnect reorganization algorithm for reduction stages in parallel multipliers. It aims at minimizing power consumption for given static probabilities at the pri...
DAC
2005
ACM
15 years 10 months ago
2005
ACM
This paper presents a novel repeater insertion algorithm for the power minimization of realistic interconnect trees under given timing budgets. Our algorithm judiciously combines ...
CHES
2004
Springer
15 years 3 months ago
2004
Springer
Dual-rail encoding, return-to-spacer protocol and hazard-free logic can be used to resist differential power analysis attacks by making the power consumption independent of process...