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» Genetic Simulation for Finite State Machine Identification
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64
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COMCOM
1999
124views more  COMCOM 1999»
14 years 9 months ago
Minimizing the Cost of Fault Location when Testing from a Finite State Machine
If a test does not produce the expected output, the incorrect output may have been caused by an earlier state transfer failure. Ghedamsi and von Bochmann [1992] and Ghedamsi et al...
Robert M. Hierons
ICCD
1995
IEEE
119views Hardware» more  ICCD 1995»
15 years 1 months ago
Extraction of finite state machines from transistor netlists by symbolic simulation
– This paper describes a new technique for extracting clock-level finite state machines(FSMs) from transistor netlists using symbolic simulation. The transistor netlist is prepr...
Manish Pandey, Alok Jain, Randal E. Bryant, Derek ...
ANSS
2001
IEEE
15 years 1 months ago
Fault Identification in Networks by Passive Testing
In this paper, we employ the finite state machine (FSM) model for networks to investigate fault identification using passive testing. First, we introduce the concept of passive te...
Raymond E. Miller, Khaled A. Arisha
EH
1999
IEEE
125views Hardware» more  EH 1999»
15 years 1 months ago
Improving Correctness of Finite-State Machine Synthesis from Multiple Partial Input/Output Sequences
Our previous work focused on the synthesis of sequential circuits based on a partial input/output sequence. As the behavioural description of the target circuit is not known the c...
Prabhas Chongstitvatana, Chatchawit Aporntewan
84
Voted
VTS
1998
IEEE
97views Hardware» more  VTS 1998»
15 years 1 months ago
On the Identification of Optimal Cellular Automata for Built-In Self-Test of Sequential Circuits
This paper presents a BIST architecture for Finite State Machines that exploits Cellular Automata (CA) as pattern generators and signature analyzers. The main advantage of the pro...
Fulvio Corno, Nicola Gaudenzi, Paolo Prinetto, Mat...