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» Geometric programming for circuit optimization
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TCAD
2002
91views more  TCAD 2002»
14 years 11 months ago
Retiming and clock scheduling for digital circuit optimization
Abstract--This paper investigates the application of simultaneous retiming and clock scheduling for optimizing synchronous circuits under setup and hold constraints. Two optimizati...
Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman
81
Voted
ICCAD
1998
IEEE
95views Hardware» more  ICCAD 1998»
15 years 4 months ago
Efficient analog circuit synthesis with simultaneous yield and robustness optimization
This paper presents an efficient statistical design methodology that allows simultaneous sizing for performance and optimization for yield and robustness of analog circuits. The s...
Geert Debyser, Georges G. E. Gielen
ICCAD
1997
IEEE
90views Hardware» more  ICCAD 1997»
15 years 3 months ago
A hierarchical decomposition methodology for multistage clock circuits
† This paper describes a novel methodology to automate the design of the interconnect distribution for multistage clock circuits. We introduce two key ideas. First, a hierarchica...
Gary Ellis, Lawrence T. Pileggi, Rob A. Rutenbar
ISLPED
2004
ACM
169views Hardware» more  ISLPED 2004»
15 years 5 months ago
Delay optimal low-power circuit clustering for FPGAs with dual supply voltages
This paper presents a delay optimal FPGA clustering algorithm targeting low power. We assume that the configurable logic blocks of the FPGA can be programmed using either a high s...
Deming Chen, Jason Cong
ICCAD
2009
IEEE
144views Hardware» more  ICCAD 2009»
14 years 9 months ago
Virtual probe: A statistically optimal framework for minimum-cost silicon characterization of nanoscale integrated circuits
In this paper, we propose a new technique, referred to as virtual probe (VP), to efficiently measure, characterize and monitor both inter-die and spatially-correlated intra-die va...
Xin Li, Rob A. Rutenbar, R. D. (Shawn) Blanton