This paper presents a completely systematic design procedure for asynchronous controllers. The initial step is the construction of a signal transition graph (STG, an interpreted P...
Gate sizing in VLSI design is a widely-used method for power or area recovery subject to timing constraints. Several previous works have proposed gate sizing heuristics for power ...
High-level programming languages offer significant expressivity but provide little or no guarantees about resource use. Resourcebounded languages -- such as hardware-description l...
This paper considers the problem of determining an optimal clock skew schedule for a synchronous VLSI circuit. A novel formulation of clock skew scheduling as a constrained quadrat...
We propose a principled account on multiclass spectral clustering. Given a discrete clustering formulation, we first solve a relaxed continuous optimization problem by eigendecomp...