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» Geometric programming for circuit optimization
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ISCAS
1994
IEEE
104views Hardware» more  ISCAS 1994»
15 years 5 months ago
A Graph-Theoretic Approach to Clock Skew Optimization
This paper addresses the problem of minimizing the clock period of a circuit by optimizingthe clock skews. We incorporate uncertainty factors and present a formulation that ensure...
Rahul B. Deokar, Sachin S. Sapatnekar
DAC
1997
ACM
15 years 5 months ago
CLIP: An Optimizing Layout Generator for Two-Dimensional CMOS Cells
We present a novel technique CLIP for optimizing both the height and width of CMOS cell layouts in the two-dimensional (2D) style. CLIP is based on integer-linear programming (ILP...
Avaneendra Gupta, John P. Hayes
ASPDAC
2005
ACM
89views Hardware» more  ASPDAC 2005»
15 years 3 months ago
Optimal placement by branch-and-price
— Circuit placement has a large impact on all aspects of performance; speed, power consumption, reliability, and cost are all affected by the physical locations of interconnected...
Pradeep Ramachandaran, Ameya R. Agnihotri, Satoshi...
DAC
2000
ACM
16 years 2 months ago
Formal verification of iterative algorithms in microprocessors
Contemporary microprocessors implement many iterative algorithms. For example, the front-end of a microprocessor repeatedly fetches and decodes instructions while updating interna...
Mark Aagaard, Robert B. Jones, Roope Kaivola, Kath...
DAC
2006
ACM
16 years 2 months ago
Optimal cell flipping in placement and floorplanning
In a placed circuit, there are a lot of movable cells that can be flipped to further reduce the total wirelength, without affecting the original placement solution. We aim at solv...
Chiu-Wing Sham, Evangeline F. Y. Young, Chris C. N...