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» Geometric programming for circuit optimization
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ICCAD
1998
IEEE
105views Hardware» more  ICCAD 1998»
15 years 4 months ago
Fanout optimization under a submicron transistor-level delay model
In this paper we present a new fanout optimization algorithm which is particularly suitable for digital circuits designed with submicron CMOS technologies. Restricting the class o...
Pasquale Cocchini, Massoud Pedram, Gianluca Piccin...
TCAD
2008
93views more  TCAD 2008»
14 years 11 months ago
Chip Optimization Through STI-Stress-Aware Placement Perturbations and Fill Insertion
Starting at the 65-nm node, stress engineering to improve the performance of transistors has been a major industry focus. An intrinsic stress source--shallow trench isolation (STI)...
Andrew B. Kahng, Puneet Sharma, Rasit Onur Topalog...
DAC
2007
ACM
16 years 23 days ago
Optimal Selection of Voltage Regulator Modules in a Power Delivery Network
High efficiency low voltage DC-DC conversion is a key enabler to the design of power-efficient integrated circuits. Typically a star configuration of the DC-DC converters, where o...
Behnam Amelifard, Massoud Pedram
ASPDAC
2007
ACM
132views Hardware» more  ASPDAC 2007»
15 years 3 months ago
Fast Decoupling Capacitor Budgeting for Power/Ground Network Using Random Walk Approach
- This paper proposes a fast and practical decoupling capacitor (decap) budgeting algorithm to optimize the power ground (P/G) network design. The new method adopts a modified rand...
Le Kang, Yici Cai, Yi Zou, Jin Shi, Xianlong Hong,...
ICCAD
1999
IEEE
120views Hardware» more  ICCAD 1999»
15 years 4 months ago
Design and optimization of LC oscillators
We present a method for optimizing and automating component and transistor sizing for CMOS LC oscillators. We observe that the performance measures can be formulated as posynomial...
Maria del Mar Hershenson, Ali Hajimiri, Sunderaraj...