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» Geometric programming for circuit optimization
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ICCD
2008
IEEE
111views Hardware» more  ICCD 2008»
15 years 8 months ago
Test-access mechanism optimization for core-based three-dimensional SOCs
— Test-access mechanisms (TAMs) and test wrappers (e.g., the IEEE Standard 1500 wrapper) facilitate the modular testing of embedded cores in a core-based system-on-chip (SOC). Su...
Xiaoxia Wu, Yibo Chen, Krishnendu Chakrabarty, Yua...
DAC
1995
ACM
15 years 3 months ago
A Transformation-Based Approach for Storage Optimization
High-level synthesis (HLS) has been successfully targeted towards the digital signal processing (DSP) domain. Both application-speci c integrated circuits (ASICs) and application-...
Wei-Kai Cheng, Youn-Long Lin
DAC
2005
ACM
15 years 1 months ago
Multi-frequency wrapper design and optimization for embedded cores under average power constraints
This paper presents a new method for designing test wrappers for embedded cores with multiple clock domains. By exploiting the use of multiple shift frequencies, the proposed meth...
Qiang Xu, Nicola Nicolici, Krishnendu Chakrabarty
VLSID
2007
IEEE
120views VLSI» more  VLSID 2007»
16 years 4 days ago
Statistical Leakage and Timing Optimization for Submicron Process Variation
Leakage power is becoming a dominant contributor to the total power consumption and dual-Vth assignment is an efficient technique to decrease leakage power, for which effective de...
Yuanlin Lu, Vishwani D. Agrawal
CCCG
2003
15 years 1 months ago
An algorithm for the MaxMin area triangulation of a convex polygon
Given a convex polygon in the plane, we are interested in triangulations of its interior, i.e. maximal sets of nonintersecting diagonals that subdivide the interior of the polygon...
J. Mark Keil, Tzvetalin S. Vassilev