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» Geometric programming for circuit optimization
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ISQED
2006
IEEE
147views Hardware» more  ISQED 2006»
15 years 5 months ago
Compact Reduced Order Modeling for Multiple-Port Interconnects
— In this paper, we propose an efficient model order reduction (MOR) algorithm, called MTermMOR, for modeling interconnect circuits with large number of external ports. The prop...
Pu Liu, Sheldon X.-D. Tan, Bruce McGaughy, Lifeng ...
GECCO
2003
Springer
120views Optimization» more  GECCO 2003»
15 years 5 months ago
Multi-FPGA Systems Synthesis by Means of Evolutionary Computation
Abstract. Multi-FPGA systems (MFS) are used for a great variety of applications, for instance, dynamically re-configurable hardware applications, digital circuit emulation, and num...
José Ignacio Hidalgo, Francisco Ferná...
EUROPAR
2000
Springer
15 years 3 months ago
BitValue Inference: Detecting and Exploiting Narrow Bitwidth Computations
We present a compiler algorithm called BitValue, which can discover both unused and constant bits in dusty-deck C programs. BitValue uses forward and backward dataflow analyses, ge...
Mihai Budiu, Majd Sakr, Kip Walker, Seth Copen Gol...
COMGEO
2008
ACM
14 years 12 months ago
Optimal location of transportation devices
We consider algorithms for finding the optimal location of a simple transportation device, that we call a moving walkway, consisting of a pair of points in the plane between which ...
Jean Cardinal, Sébastien Collette, Ferran H...
TCAD
2010
88views more  TCAD 2010»
14 years 6 months ago
Stress Aware Layout Optimization Leveraging Active Area Dependent Mobility Enhancement
Starting from the 90nm technology node, process induced stress has played a key role in the design of highperformance devices. The emergence of source/drain silicon germanium (S/D ...
Ashutosh Chakraborty, Sean X. Shi, David Z. Pan