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» Geometric programming for circuit optimization
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ISCAS
2006
IEEE
101views Hardware» more  ISCAS 2006»
15 years 5 months ago
Neuromimetic ICs and system for parameters extraction in biological neuron models
—This paper presents an analog neuromimetic integrated circuit and an associated system dedicated for experiments of parameters extraction in biological neuron models. The IC bas...
Sylvain Saïghi, Yannick Bornat, Jean Tomas, S...
IPPS
2003
IEEE
15 years 5 months ago
Task Graph Scheduling Using Timed Automata
In this paper we develop a methodology for treating the problem of scheduling partially-ordered tasks on parallel machines. Our framework is based on the timed automaton model, or...
Yasmina Abdeddaïm, Abdelkarim Kerbaa, Oded Ma...
ICCD
2007
IEEE
322views Hardware» more  ICCD 2007»
15 years 8 months ago
Voltage drop reduction for on-chip power delivery considering leakage current variations
In this paper, we propose a novel on-chip voltage drop reduction technique for on-chip power delivery networks of VLSI systems in the presence of variational leakage current sourc...
Jeffrey Fan, Ning Mi, Sheldon X.-D. Tan
ISPD
2009
ACM
141views Hardware» more  ISPD 2009»
15 years 6 months ago
A faster approximation scheme for timing driven minimum cost layer assignment
As VLSI technology moves to the 65nm node and beyond, interconnect delay greatly limits the circuit performance. As a critical component in interconnect synthesis, layer assignmen...
Shiyan Hu, Zhuo Li, Charles J. Alpert
DAC
2005
ACM
15 years 1 months ago
How accurately can we model timing in a placement engine?
This paper presents a novel placement algorithm for timing optimization based on a new and powerful concept, which we term differential timing analysis. Recognizing that accurate ...
Amit Chowdhary, Karthik Rajagopal, Satish Venkates...