241 search results - page 38 / 49 » Geometry of synthesis: a structured approach to VLSI design |
113
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DAC
2001
ACM
16 years 2 months ago
2001
ACM
Many tasks in CAD, such as equivalence checking, property checking, logic synthesis, and false paths analysis require efficient Boolean reasoning for problems derived from circuit...
125
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ICCAD
2000
IEEE
15 years 6 months ago
2000
IEEE
Abstract— Deep submicron technology scaling has two major ramifications on the design process. First, reduced feature size significantly increases wire delay, thus resulting in...
108
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VLSID
2002
IEEE
16 years 2 months ago
2002
IEEE
Verification is one of the most complex and expensive tasks in the current Systems-on-Chip (SOC) design process. Many existing approaches employ a bottom-up approach to pipeline v...
131
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VIS
2004
IEEE
16 years 3 months ago
2004
IEEE
Vortex breakdowns and flow recirculation are essential phenomena in aeronautics where they appear as a limiting factor in the design of modern aircrafts. Because of the inherent i...
118
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DAC
2004
ACM
16 years 2 months ago
2004
ACM
Long design cycles due to the inability to predict silicon realities is a well-known problem that plagues analog/RF integrated circuit product development. As this problem worsens...