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» Geometry of synthesis: a structured approach to VLSI design
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GLVLSI
2006
IEEE
124views VLSI» more  GLVLSI 2006»
15 years 3 months ago
Dominator-based partitioning for delay optimization
Most of the logic synthesis algorithms are not scalable for large networks and, for this reason, partitioning is often applied. However traditional mincut-based partitioning techn...
David Bañeres, Jordi Cortadella, Michael Ki...
112
Voted
GLVLSI
2002
IEEE
160views VLSI» more  GLVLSI 2002»
15 years 2 months ago
Computing walsh, arithmetic, and reed-muller spectral decision diagrams using graph transformations
Spectral techniques have found many applications in computeraided design, including synthesis, verification, and testing. Decision diagram representations permit spectral coeffici...
Whitney J. Townsend, Mitchell A. Thornton, Rolf Dr...
ISCAS
2011
IEEE
288views Hardware» more  ISCAS 2011»
14 years 1 months ago
Multi-layer parallel decoding algorithm and vlsi architecture for quasi-cyclic LDPC codes
—We propose a multi-layer parallel decoding algorithm and VLSI architecture for decoding of structured quasi-cyclic low-density parity-check codes. In the conventional layered de...
Yang Sun, Guohui Wang, Joseph R. Cavallaro
83
Voted
VLSID
2003
IEEE
253views VLSI» more  VLSID 2003»
15 years 10 months ago
High Level Synthesis from Sim-nML Processor Models
The design of modern complex embedded systems require a high level of abstraction of the design. The SimnML[1] is a specification language to model processors for such designs. Se...
Souvik Basu, Rajat Moona
72
Voted
ICRA
1998
IEEE
100views Robotics» more  ICRA 1998»
15 years 1 months ago
Design for Tolerance of Electro-Mechanical Assemblies
Tolerancing decisions can profoundly impact the quality and cost of electro-mechanical assemblies. Existing approaches to tolerance analysis and synthesis in design entail detailed...
Rachuri Sudarsan, Y. Narahari, Kevin W. Lyons, Ram...