41 search results - page 4 / 9 » Glitch Analysis and Reduction in Register Transfer Level |
CODES
2009
IEEE
15 years 1 months ago
2009
IEEE
In this paper, we propose an effective automatic generation approach for a Cycle-Count Accurate Memory Model (CCAMM) from the Clocked Finite State Machine (CFSM) of the Cycle Accu...
94
Voted
DAC
2008
ACM
14 years 11 months ago
2008
ACM
Clock skew scheduling has been traditionally considered as a tool for improving the clock period in a sequential circuit. Timing slack is "stolen" from fast combinationa...
CODES
2005
IEEE
15 years 3 months ago
2005
IEEE
This paper presents a novel approach for multiprocess synthesis supporting well-tailored module integration at system level. The goal is to extend the local scope of existing arch...
CODES
2007
IEEE
15 years 3 months ago
2007
IEEE
This paper proposes a low power VLIW processor generation method by automatically extracting non-redundant activation conditions of pipeline registers for clock gating. It is impo...
82
Voted
DAC
2006
ACM
15 years 3 months ago
2006
ACM
Several emerging Design-for-Debug (DFD) methodologies are addressing silicon debug by making internal signal values and other data observable. Most of these methodologies require ...