25 search results - page 2 / 5 » Global Multi-Threaded Instruction Scheduling |
DTJ
1998
14 years 9 months ago
1998
MICRO
1998
IEEE
15 years 1 months ago
1998
IEEE
Path profiles record the frequencies of execution paths through a program. Until now, the best global instruction schedulers have relied upon profile-gathered frequencies of condi...
ISCA
2003
IEEE
15 years 2 months ago
2003
IEEE
To achieve high instruction throughput, instruction schedulers must be capable of producing high-quality schedules that maximize functional unit utilization while at the same time...
IPPS
2006
IEEE
15 years 3 months ago
2006
IEEE
The industry is rapidly moving towards the adoption of Chip Multi-Processors (CMPs) of Simultaneous MultiThreaded (SMT) cores for general purpose systems. The most prominent use o...
HIPEAC
2007
Springer
15 years 3 months ago
2007
Springer
Caches are designed to provide the best tradeoff between access speed and capacity for a set of target applications. Unfortunately, different applications, and even different phas...