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ISVLSI
2008
IEEE
173views VLSI» more  ISVLSI 2008»
15 years 5 months ago
Hermes-GLP: A GALS Network on Chip Router with Power Control Techniques
The evolution of deep submicron technologies allows the development of increasingly complex Systems on a Chip (SoC). However, this evolution is rendering less viable some well-est...
Julian J. H. Pontes, Matheus T. Moreira, Rafael So...
ICPPW
2005
IEEE
15 years 4 months ago
A Practical Approach to the Rating of Barrier Algorithms Using the LogP Model and Open MPI
Large–scale parallel applications performing global synchronization may spend a significant amount of execution time waiting for the completion of a barrier operation. Conseque...
Torsten Hoefler, Lavinio Cerquetti, Torsten Mehlan...
PPOPP
1993
ACM
15 years 2 months ago
Integrating Message-Passing and Shared-Memory: Early Experience
This paper discusses some of the issues involved in implementing a shared-address space programming model on large-scale, distributed-memory multiprocessors. While such a programm...
David A. Kranz, Kirk L. Johnson, Anant Agarwal, Jo...
EMSOFT
2007
Springer
15 years 2 months ago
Necessary and sufficient conditions for deterministic desynchronization
Synchronous reactive formalisms associate concurrent behaviors to precise schedules on global clock(s). This allows a non-ambiguous notion of "absent" signal, which can ...
Dumitru Potop-Butucaru, Robert de Simone, Yves Sor...
DAC
2009
ACM
15 years 2 months ago
NUDA: a non-uniform debugging architecture and non-intrusive race detection for many-core
Traditional debug methodologies are limited in their ability to provide debugging support for many-core parallel programming. Synchronization problems or bugs due to race conditio...
Chi-Neng Wen, Shu-Hsuan Chou, Tien-Fu Chen, Alan P...