15 search results - page 1 / 3 » Global Variable Promotion: Using Registers to Reduce Cache P... |
CC
2002
Springer
13 years 8 months ago
2002
Springer
Global variable promotion, i.e. allocating unaliased globals to registers, can significantly reduce the number of memory operations. This results in reduced cache activity and less...
CF
2005
ACM
13 years 11 months ago
2005
ACM
Power consumption within the memory hierarchy grows in importance as on-chip data caches occupy increasingly greater die area. Among dynamic power conservation schemes, horizontal...
DATE
2004
IEEE
14 years 21 days ago
2004
IEEE
: Static energy dissipation in cache memories will constitute an increasingly larger portion of total microprocessor energy dissipation due to nanoscale technology characteristics ...
IEEEPACT
2003
IEEE
14 years 2 months ago
2003
IEEE
We present a technique for reducing the power dissipation in the course of writebacks and committments in a datapath that uses a dedicated architectural register file (ARF) to hol...
ISLPED
2003
ACM
14 years 2 months ago
2003
ACM
Modern superscalar processors implement precise interrupts by using the Reorder Buffer (ROB). In some microarchitectures , such as the Intel P6, the ROB also serves as a repositor...